1. Field of the Invention
The invention relates to the field of high speed digital electronic circuitry, more particularly to electrical delay lines and methods for their design.
2. Description of the Prior Art
In the design of high speed electronic circuits it is often essential that the difference in the arrival times between two or more electrical signals at a given point in the circuit be less than some prespecified amount. When this cannot be readily achieved by other means, it becomes necessary to insert some electrical delay in the path(s) of the early arriving signal(s).
One means of providing the needed delay is through use of a delay line. This consists essentially of an appropriate length of an interconnect line. For reasons of packaging efficiency it is necessary to shape the delay line into a form that occupies as little space as possible. A shape that is widely used in the electronics industry for this purpose is the so-called serpentine. The conducting wire that constitutes a serpentine delay line winds back and forth in the same plane to create a series of parallel sections that are connected at alternating ends as shown in FIG. 1. Original signal 1, emerging from source resistance, R.sub.s, 2 enters delay line 3 sending to loading resistance, R.sub.1, 4. The overall dimensions of such a delay line would, in general, be between 0.5 and 13 cm. separation by between 10 microns and 0.3 cm., for a total line length of between 5 and 117 cm.
Typically the spacing 6 between adjoining sections of a serpentine delay line would be about 0.1 mm. which is close enough for significant cross-talk between sections to occur. That is, a small amount of the signal that is travelling down a given section will be induced in adjoining sections. In the serpentine design the timing is such that the signals induced in the various sections, as the main signal travels past them, all arrive at the same time at the end of the delay line before the real signal, producing a false signal that can be above the threshold voltage of the digital circuit.
An example of this is shown in FIG. 2. Curve 7 is for a serpentine delay line of length 5 cm. while curve 8 is for a 10 cm. line. Curve 9 shows the shape and timing of the sending-end signal. These curves were created through simulation, as reported by Wu and Chao in `laddering wave in serpentine delay line` published in the proceedings of the IEEE EPEP Conference held in California in September 1994 (pages 124 to 127). The intended delays for the 5 cm. and 10 cm. lines were 3.0 and 6.0 nsec respectively, whereas, as can be seen, significant rises in the arriving signals are already occuring after 2.3 and 4.6 nsecs respectively. The same data obtained through actual measurements are shown in FIG. 3 and can be seen to be very similar to the simulation data. Curve 10 corresponds to curve 8 in FIG. 2 and curve 11 corresponds to curve 7 in FIG. 2.
The highly undesirable early-arriving false signal effect could, in principle, be mitigated through a reduction in the cross-talk between the various sections of the serpentine delay line. Unfortunately, the two ways to accomplish this are to slow down the circuits involved or to increase the spacing between the various sections of the serpentine line and neither solution is acceptable.